Modeling an FSM in implicit style is a more powerful, abstract and
concise method to define an FSM as compared to explicit coding
style. Implicit style models FSMs in terms of activities at
different clock cycles without the need for defining state
transitions explicitly and partitioning the code into combinational
(next state and output logic) and sequential (present state
register) segments. However, implicit style registers all FSM
outputs by default; unlike explicit style where the designer can
choose to make the outputs combinational or registered. These
flip-flops delay the outputs by one clock cycle and assert them for
one or more extra cycles in multi-cycle operations, as compared to
explicit style. In addition, Mealy outputs in implicit FSMs cannot
respond immediately to changes in input. We developed a methodology
that removes the output flip-flops after synthesis. This
modification process involves editing EDIF files generated by
third-party synthesizers (such as FPGA Express from Synopsys) and
providing the modified EDIF file to the place-and-route tool. This
methodology ensures that a modified implicit FSM operates the same
way as an explicit FSM, after synthesis.
Is the information for this product incomplete, wrong or inappropriate?
Let us know about it.
Does this product have an incorrect or missing image?
Send us a new image.
Is this product missing categories?
Add more categories.
Review This Product
No reviews yet - be the first to create one!