Your cart

Your cart is empty

Books > Computing & IT > General theory of computing > Systems analysis & design

Buy Now

Verification Methodology Manual for SystemVerilog (Hardcover, 2006 ed.) Loot Price: R4,885
Discovery Miles 48 850
Verification Methodology Manual for SystemVerilog (Hardcover, 2006 ed.): Janick Bergeron, Eduard Cerny, Alan Hunter, Andy...

Verification Methodology Manual for SystemVerilog (Hardcover, 2006 ed.)

Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale

 (sign in to rate)
Loot Price R4,885 Discovery Miles 48 850 | Repayment Terms: R447 pm x 12*

Bookmark and Share

Expected to ship within 7 - 11 working days

Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies. Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform. Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the SystemVerilog Verification Methodology Manual (VMM). their customers. The SystemVerilog VMM is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems. This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the SystemVerilog VMM will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.


Imprint: Springer-Verlag New York
Country of origin: United States
Release date: September 2005
First published: November 2005
Authors: Janick Bergeron • Eduard Cerny • Alan Hunter • Andy Nightingale
Dimensions: 235 x 155 x 28mm (L x W x T)
Format: Hardcover
Pages: 503
Edition: 2006 ed.
ISBN-13: 978-0-387-25538-5
Categories: Books > Computing & IT > General theory of computing > Systems analysis & design
LSN: 0-387-25538-9
Barcode: 9780387255385

Is the information for this product incomplete, wrong or inappropriate? Let us know about it.

Does this product have an incorrect or missing image? Send us a new image.

Is this product missing categories? Add more categories.

Review This Product

No reviews yet - be the first to create one!