VLSI Test Principles and Architectures - Design for Testability (Hardcover, New)

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This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
. Most up-to-date coverage of design for testability.
. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
. Lecture slides and exercise solutions for all chapters are now available.
. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

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Product Description

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
. Most up-to-date coverage of design for testability.
. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
. Lecture slides and exercise solutions for all chapters are now available.
. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

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Product Details

General

Imprint

Morgan Kaufmann Publishers In

Country of origin

United States

Release date

August 2006

Availability

Expected to ship within 12 - 17 working days

First published

June 2006

Authors

, ,

Contributors

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Dimensions

235 x 191 x 51mm (L x W x T)

Format

Hardcover

Pages

808

Edition

New

ISBN-13

978-0-12-370597-6

Barcode

9780123705976

Categories

LSN

0-12-370597-5



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